Modern processors often access memory modules using addresses. Such memory modules include L1 and L2 caches, as well as Static Random Access Memory (SRAM) modules. These addresses are employed to activate certain wordlines, which allow conductivity between activated or deactivated cells within subarrays and bitlines coupled thereto. Conventional decoders typically include an initial decode stage (or “predecode” stage), as well as a final decode stage where the decoded addresses are used to activate selected wordlines to generate data from the memory module.
However, in the final wordline decode stage, defects in the wordline selected by the address may cause the intended subarray of cells to fail, and thus the data to be corrupt. Among the available techniques used to avoid wordline defects, wordline/bitline redundancy control is perhaps the most commonly used. In conventional redundancy control, when an address points to a wordline found to contain a defect, a mechanism within the final decode stage causes a different wordline to be selected. In high performance memory cases, shift registers, or other similar devices, are employed in the final decode stage to accomplish this “shifting” of the selected wordlines. Multiple shift registers are usually employed, one for each of the wordlines found in the final decode stage. For example, Bit 1 is programmed in the shift register, and the corresponding wordline is shifted by a steering circuit. The steering circuit is usually a multiplexer (MUX). If 2 adjacent wordlines need to be fixed by a one-bit shift scheme, one is shifted up and the other is shifted down. By shifting the wordline, the defective wordline originally selected is bypassed altogether. In addition, for defects found in bitlines, write and read paths are shifted to bypath a defective bitline, just as is done for defective wordlines.
Unfortunately, conventional shifting techniques found in the existing art are not without their problems. For example, in techniques where shifting is accomplished in the decoding stage of the addresses, a large amount of logic is typically required in order to overcome defects detected in wordlines by employing redundant wordlines. Those who are skilled in the art understand that increasing the amount of logic not only increases the cost of devices, but also increases the complexity of the circuits involved. Furthermore, as the logic employed to achieve a desired result is increased, more time to reach that result is required. Of course, increasing delay time usually slows the overall operation of the device.
In other approaches, multiple shift registers are coupled together in a series connection, and then coupled to the multiple wordlines found in the decoder. However, with a series connection between all of the shift registers, when the defective wordlines are adjacent, one of the wordlines is typically set down and the other is set up. Unfortunately, with this configuration, at least a 3:1 multiplexer must be employed to allow the adjacent wordline fix, which usually results in a heavier, more complex circuit. Moreover, the stacked layout of the series-coupled registers may result in wire-crossing when overcoming multiple defective non-adjacent wordlines. More specifically, this is the case because “jumping” some of the series-coupled shift registers associated with the non-adjacent defective wordlines is typically required. Accordingly, a need exists for a decoder for use with high frequency deep pipeline memory systems capable of overcoming wordline defects without suffering from the deficiencies found in conventional decoders.